ASML’s High-NA EUV machines cost roughly $400 million each. Intel is already using the technology on selected production layers, Samsung plans to bring it into advanced DRAM manufacturing by 2028, and TSMC intends to use it for advanced-node production starting in 2030.
At first glance, that sounds like a simple semiconductor story: chips are getting smaller, so fabs need a more powerful lithography machine.
I think that misses the more interesting part.
The real question is not whether High-NA EUV is better than conventional EUV. It clearly offers finer resolution. The question is when a $400 million scanner becomes cheaper than continuing to manufacture advanced chips without one.
That crossover is starting to appear. As conventional EUV is pushed further, manufacturers can preserve it with more complicated patterning and additional process steps. High-NA offers another option: spend much more on the scanner, but simplify some of the work around it.
That is why 2026 matters. The industry is moving from debating whether High-NA will eventually be necessary to deciding which layers need it first, and when the economics justify the switch.
HIGH-NA AT A GLANCE
The $400 Million Price Tag Is Only Half the Cost Question
Today's mainstream EUV systems use a numerical aperture of 0.33. ASML's newer EXE High-NA platform raises that to 0.55.
The EXE:5200B offers 8 nm resolution and, according to ASML, can print features 1.7 times smaller in a single exposure than its NXE systems, supporting roughly 2.9 times higher transistor density. ASML's argument is not just that the image is finer. The company says High-NA can reduce process complexity in high-volume manufacturing and increase wafer output.
That second part is what makes the economics interesting.
When a critical pattern becomes too difficult to print in one exposure, a chipmaker can sometimes keep using existing lithography by splitting the work across multiple patterning steps. That avoids buying the newest scanner immediately, but the saving is not free.
More patterning can mean more masks, more deposition and etching, longer cycle times and more opportunities for overlay errors or defects. Exactly how much High-NA removes depends on the layer and process, so it would be wrong to treat every extra exposure as automatically eliminated.
Still, the comparison changes.
A fab manager is not really choosing between a $400 million machine and a cheaper machine. The relevant comparison is between two complete manufacturing flows.
One flow uses an extremely expensive High-NA scanner.
The other may use cheaper, mature equipment but require increasing complexity around it.
That is the part of the High-NA story I would watch. A machine can look absurdly expensive in isolation and still become rational if the process it replaces has become expensive enough.
THE MANUFACTURING TRADE-OFF
Use High-NA
Pay much more for the scanner, while potentially simplifying some of the patterning work around the critical layer.
Extend conventional EUV
Keep mature equipment longer, but potentially accept more masks, patterning steps, cycle time and process complexity.
Intel Has Already Put That Argument Into Production
Intel is the strongest evidence that High-NA has moved beyond an R&D demonstration.
Intel Foundry and ASML said in September that more than one million wafers had been processed across tool certification, testing, R&D and production. High-NA is now being used on selected layers for a subset of Intel Core Ultra Series 3 processors, code-named Panther Lake. Intel says overlay, throughput and availability are meeting its expectations.
The wording matters.
Intel is not manufacturing every Panther Lake layer with High-NA. It does not need to.
Advanced fabs already mix lithography technologies according to what each layer requires. High-NA only has to make sense on the layers where its extra resolution or simpler patterning creates enough value.
That makes Intel's deployment more useful as evidence than a blanket claim that High-NA has “replaced” conventional EUV.
It has not.
What Intel has demonstrated is more specific: there are already commercial production layers where using High-NA is practical enough to justify putting it into the flow.
For a technology this expensive and this complicated, that is a meaningful threshold.
Samsung and TSMC Show There Is No Single High-NA Deadline
The next mistake would be to assume every leading chipmaker should therefore adopt High-NA at the same time.
They should not.
Samsung says it plans to introduce High-NA EUV into advanced DRAM high-volume manufacturing by 2028, which would be the first such use in memory production. Samsung specifically points to improved resolution, process simplification and efficiency as reasons for the transition.
TSMC is taking a slower route. It says it intends to use High-NA in high-volume manufacturing for advanced nodes starting in 2030 and expects the number of High-NA layers to rise as future transistor architectures become more complex.
SK hynix is also targeting High-NA adoption for DRAM from 2028, according to Reuters.
| Company | High-NA position | Current timing |
| Intel | Used on selected commercial logic layers | In production |
| Samsung | Planned for advanced DRAM high-volume manufacturing | By 2028 |
| SK hynix | Planned for DRAM | From 2028 |
| TSMC | Planned for advanced-node high-volume manufacturing | Starting 2030 |
I would not read those different dates as disagreement over whether High-NA works.
They say more about the economics of each manufacturer's process.
A company with mature conventional EUV recipes, strong yields and enough room to extend its current process has every reason to keep using equipment it already understands. Installed tools, process knowledge and engineering experience have value too.
High-NA therefore carries the burden of proof. Better resolution alone is not enough. It has to deliver enough improvement in density, process simplicity, yield, cycle time or future scaling to justify inserting an entirely new lithography platform.
That threshold will arrive at different times for DRAM, logic and individual process layers.
In other words, there is no semiconductor-industry High-NA deadline. There are several economic crossover points.
The Catch: High-NA Solves One Problem and Creates Another
There is also a good reason not to treat High-NA as an easy upgrade.
Its anamorphic optical system uses an exposure field half the size of conventional NXE systems. ASML designed faster wafer and reticle stages to compensate for that architecture, but the smaller field becomes important when manufacturers want to expose very large chip designs.
That is particularly relevant for very large chips.
AI accelerators and data-center processors can be physically large devices. If a design exceeds the available High-NA exposure field, manufacturers may need to divide the pattern and stitch sections together.
That creates exactly the kind of manufacturing complexity High-NA is supposed to reduce.
ASML is therefore working with major semiconductor manufacturers on a larger 12-inch photomask platform designed to remove those stitching constraints.
Samsung says moving from the industry's long-established 6-inch mask format toward 12-inch masks could increase fab productivity, reduce manufacturing costs and allow larger advanced designs to capture more of High-NA's benefits.
Reuters reports that ASML expects a pilot line for the larger-mask approach around 2031, followed by high-volume deployment around 2033. The company estimates the change could improve system productivity by roughly 40%.
That timeline creates an important distinction.
High-NA can enter manufacturing before the 12-inch mask ecosystem is complete.
But the larger-mask transition could determine how broadly the technology eventually spreads across very large AI processors.
High-NA Does Not Kill Conventional EUV
There is an easy mistake to make here.
If High-NA is entering production, it may sound as though ASML's existing EUV platform is suddenly obsolete.
It is not.
Conventional EUV remains extraordinarily capable, and ASML continues increasing its productivity. High-NA will initially be justified only on layers where its resolution or process simplification produces sufficient economic value.
That means leading-edge fabs are likely to operate mixed lithography environments.
Some layers may use High-NA.
Others will continue using conventional EUV.
Less demanding layers will continue using older deep-ultraviolet lithography.
The semiconductor industry does not replace every tool when a new lithography generation arrives. It inserts the most expensive technology only where the manufacturing economics justify it.
That matters for ASML too.
Reuters reported that demand for the company's current EUV systems has nearly filled available capacity through 2027 even as customers begin moving toward High-NA.
The transition therefore looks more additive than immediately substitutive.
What Could Still Slow High-NA Adoption?
The transition is not risk-free.
First, the machines are extremely expensive. High-NA has to create enough value at the wafer level to justify that capital intensity.
Second, resolution is only one part of lithography. Resist performance, overlay, defectivity, masks, inspection systems and process control all need to mature alongside the scanner.
Third, the smaller exposure field complicates production of large dies until stitching techniques or larger masks improve.
Fourth, conventional EUV continues getting better.
That last point may be the most underrated counterargument.
High-NA does not compete against a frozen 2024 version of EUV. It competes against a conventional EUV platform whose throughput, availability and process knowledge continue improving.
That can keep pushing the economic crossover point further out for some manufacturers and some layers.
So the question is not whether High-NA has superior resolution.
That is already established.
The question is whether it can consistently produce better economics at production scale.
The Bigger Shift Is From Resolution to Manufacturing Economics
The most interesting thing about High-NA in 2026 is therefore not the optics.
It is the change in customer behavior.
Intel has moved selected layers into production.
Samsung has attached a concrete 2028 high-volume DRAM target to the technology.
TSMC has put High-NA on its advanced manufacturing roadmap rather than treating it as an open-ended research option.
And ASML is already working on the next constraint: the mask and exposure-field architecture needed to make High-NA more productive for large chips.
That combination suggests the industry's decision has moved forward one stage.
High-NA no longer needs to prove that it can print smaller features.
It needs to prove that using those smaller features is cheaper and more productive than extending conventional EUV through increasingly complex patterning.
For the first time, several major chipmakers appear ready to test that proposition in real production.
The Signal & Scale View
The $400 million price tag is the obvious number.
It is probably not the number that determines adoption.
The more important number is the total manufacturing cost of avoiding High-NA.
As chipmakers push conventional EUV further, the alternative can require more complicated patterning, more process steps and more engineering effort. At some point, the expensive machine becomes the simpler option.
Intel appears to have crossed that threshold on selected logic layers already. Samsung believes DRAM can begin crossing it around 2028. TSMC appears comfortable waiting longer.
Those differences are not evidence that one company is right and another is wrong.
They show where each manufacturer believes the cost curve bends.
High-NA's real inflection point arrives when the cost of not using it becomes greater than the cost of buying it.
High-NA's real inflection point arrives when the cost of not using it becomes greater than the cost of buying it.
The industry is getting closer to that point.
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FAQ
Why does ASML High-NA EUV cost around $400 million?
High-NA requires a substantially more sophisticated optical and light-source system than conventional EUV. Its 0.55 numerical aperture allows finer patterns to be resolved, but achieving that performance requires extremely complex optics, precision control and supporting infrastructure.
Is High-NA EUV already being used to manufacture chips?
Yes. Intel says High-NA is already being used on selected production layers for a subset of Panther Lake processors, with more than one million wafers processed across qualification, development and production activity.
When will Samsung and TSMC use High-NA EUV?
Samsung plans to introduce High-NA into advanced DRAM high-volume manufacturing by 2028. Reuters reports that TSMC expects to deploy High-NA for advanced logic production around 2030.
Will High-NA replace existing EUV machines?
Not immediately. High-NA is likely to be inserted first on the most demanding layers, while conventional EUV and older lithography technologies remain economical for many other layers.
Why are 12-inch photomasks important for High-NA?
Current High-NA optics reduce the available exposure field. Larger masks are being developed to reduce stitching constraints, particularly for large advanced chips, while improving productivity and potentially lowering manufacturing cost.